1. Field of the Invention
This invention relates to the field of operational amplifiers (op amps), comparators, instrumentation amplifiers, and the like, and particularly to circuits designed to reduce the input bias currents in such circuits.
2. Description of the Related Art
Ideally, the input stage of a bipolar circuit such as an op amp, comparator, or an instrumentation amplifier has an input bias current IB—i.e., the amount of current which flows into or out of the circuit's input terminals—of zero. This is because the resolution of the input stage increases with a decreasing IB. For example, assume that the output current ID of a photodiode is to be amplified by an op amp configured as an inverting amplifier, with a feedback resistance R. The op amp's output voltage Vout will be given by (ID−IB)/R; i.e., the amount of photodiode current converted into an output voltage by the op amp is reduced by the magnitude of the op amp's input bias current.
The input bias current IB of a bipolar input stage is non-zero because the stage's inputs are the bases of two bipolar transistors, arranged as a differential pair. The base current of each input transistor is determined by its collector current IC and its beta value (β), with IB=IC/β. One approach to reducing IB is to use input transistors with very high betas, known as “superbeta” transistors. However, though the use of a superbeta input pair can significantly reduce IB, it cannot eliminate it—and as such, the input bias currents and input current resolution will still be less than ideal.
Another approach is shown in FIG. 1. Here, bipolar input transistors Q1 and Q2 form a differential input pair. The common emitters of Q1 and Q2 are connected to a bias current source 10, and their collectors are coupled to respective biasing transistors Q3 and Q4. A “tracking” transistor Q5 is connected in series between Q1 and Q3, and another tracking transistor Q6 is connected in series between Q2 and Q4, such that the collector-emitter circuits of Q5 and Q6 conduct the collector currents of Q1 and Q2, respectively. This results in the base currents of Q5 and Q6 tracking those of Q1 and Q2, respectively. Lateral PNP transistors Q7 and Q8 are connected to mirror the base currents of Q5 and Q6 to the bases of Q1 and Q2, respectively. Ideally, these mirrored currents effectively cancel the input bias currents of Q1 and Q2. However, due to current leakage from the base of each of the lateral PNP transistors, the collector currents of Q7 and Q8 may not accurately track the base currents of Q5 and Q6, and, hence, may not accurately cancel the bias currents of their associated input transistors.
U.S. Pat. No. 4,575,685 to Dobkin et al. is designed to overcome the leakage current problem noted above, by employing circuitry including a tracking transistor which is virtually independent of the presence or absence of leakage current. To make the tracking transistor's base current equal to that of the input transistors, the patent employs a scheme to make the collector-emitter voltages of the input and tracking transistors equal. However, the scheme used is subject to process variations that might result in unequal collector-emitter voltages, and a consequent lack of accuracy in the cancellation currents.